Field of the Invention
The present invention is related to semiconductor device manufacturing and testing, and more particularly to a test probe head for full wafer testing multiple integrated circuit (IC) chips on semiconductor wafers.
Background Description
Typical semiconductor integrated circuit (IC) chips have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a thin semiconductor wafer. Each array location is known as a die. A typical, state of the art wafer may be as large as a dinner plate or larger, e.g., 12 inches (300 millimeters or 300 mm), with projections for 18 inch (450 mm) wafers in the near future. Larger wafers allow for more die per wafer for a given die size. At the same time increased logic complexity requires a higher input/output (I/O) count.
Each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment. The surface layer of each completed chip or die is typically populated by probe-able off-chip pads for connecting to chip power and input/output (I/O) signals. Packing more function on each die typically means providing more and more I/O signals for each die, on one (a top) surface, or for a three dimensional (3D) chip structure, both (top and bottom) surfaces. Each die has at least one surface pad for each I/O signal and a number of power (supply and ground) connection pads. Increasing I/O signal and supply pad count for a given die size requires a tighter I/O pad pitch for dense I/O pad arrays, and correspondingly, a tighter test probe pitch. A typical state of the art IC wafer, for example, die may be populated by several thousand connection pads on very tight a pitch less than 50 microns (<50 μm).
Testing these tightly packed pads with or without solder balls requires very fine, delicate, tightly-packed test probes. Historically, what are known as cobra probes were used to probe down to 150 μm. Probing tightly-packed pads at 50 μm and below requires very precise probe tip geometry control and scalability. Achieving necessary probe tip precision for probing ultra-fine pitch pads has proven very difficult, and therefore, expensive. Moreover, in addition to increasing test time, repetitively shifting from one die to the next during manufacturing test, tends to degrade probe quality for these very fine, delicate, tightly-packed test probes.
Previously, multisite testing was unavailable for wafers populated by logic complex chips. Large probe heads, especially wafer level probe heads, could be used for testing low pin count memory chips, where it may be relatively easy to make contact to multiple memory dies simultaneously. However, these large probe head test cards were very expensive to build and to maintain. Moreover, these large probe heads have been limited to low pin count applications, which made the probes unattractive for high input/output (I/O) count logic chips. The poor precision of these traditional probes has made high pin count probe heads unsuitable, especially when considering the level of probe force that may be required to contact all of chip pads for chips under test.
Thus, there is a need for low cost multi-chip test probes for probing those ultra-fine pitch pads and bumps on wafers with state of the art IC chips, and in addition for probing those ultra-fine pitch pads and bumps on state of the art logic chips in a single probing.